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HM5225645F-B60 HM5225325F-B60
256M LVTTL interface SDRAM 100 MHz 1-Mword x 64-bit x 4-bank/2-Mword x 32-bit x 4-bank
PC/100 SDRAM
ADE-203-1014C (Z) Rev. 1.0 Oct. 1, 1999 Description
The Hitachi HM5225645F is a 256-Mbit SDRAM organized as 1048576-word x 64-bit x 4-bank. The Hitachi HM5225325F is a 256-Mbit SDRAM organized as 2097152-word x 32-bit x 4-bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 108 bump BGA.
Features
* * * * * * * * * Single chip wide bit solution (x 64/x 32) 3.3 V power supply Clock frequency: 100 MHz (max) LVTTL interface Extremely small foot print: 1.27 mm pitch Package: BGA (BP-108) 4 banks can operate simultaneously and independently Burst read/write operation and burst read/single write operation capability Programmable burst length: 4/8/full page 2 variations of burst sequence Sequential (BL = 4/8/full page) Interleave (BL = 4/8) Programmable CAS latency: 2/3 Byte control by DQMB
* *
HM5225645F-B60, HM5225325F-B60
* Refresh cycles: 4096 refresh cycles/64 ms * 2 variations of refresh Auto refresh Self refresh * Full page burst length capability Sequential burst Burst stop capability
Ordering Information
Type No. HM5225645FBP-B60* HM5225325FBP-B60* Frequency 100 MHz 100 MHz CAS latency 3 3 Package 14 mm x 22 mm 108 bump BGA (BP-108)
Note: 66 MHz operation at CAS latency = 2.
2
HM5225645F-B60, HM5225325F-B60
Pin Arrangement (HM5225645F)
108-bump BGA 1 A B C D E F G H J K L
DQ63
2
DQ62
3
DQ49
4
DQ48
5
VSS
6
DQ47
7
DQ46
8
DQ33
9
DQ32
DQ61
DQ60
DQ51
DQ50
VCC
DQ45
DQ44
DQ35
DQ34
DQ59
DQ58
DQ53
DQ52
VCC
DQ43
DQ42
DQ37
DQ36
DQ57 DQ MB7
DQ56 DQ MB6
DQ55
DQ54
VSS
DQ41
DQ40
DQ39 DQ MB5 RAS
DQ38 DQ MB4 WE
CKE
VCC
A12
VCC
A10
A13
A7
A5
VCC
A1
A4
VSS
A2
A3
A8
A6
VSS
A0
A11
VSS
A9
CS
M Open N P R T U
DQ MB0 DQ6
CLK
VCC DQ MB2 DQ8 DQ9 VSS DQ22 DQ23 DQ24
CAS
DQ MB1 DQ7
DQ MB3 DQ25
DQ4
DQ5
DQ10
DQ11
VCC
DQ20
DQ21
DQ26
DQ27
DQ2
DQ3
DQ12
DQ13
VCC
DQ18
DQ19
DQ28
DQ29
DQ0
DQ1
DQ14
DQ15
VSS
DQ16
DQ17
DQ30
DQ31
(Top view)
3
HM5225645F-B60, HM5225325F-B60
Pin Description (HM5225645F)
Pin name A0 to A13 Function Address input Row address Column address A0 to A11 A0 to A7
Bank select address A12/A13 (BS) DQ0 to DQ63 CS RAS CAS WE DQMB0 to DQMB7 CLK CKE VCC VSS Open Note: Data-input/output Chip select Row address strobe command Column address strobe command Write enable Byte data mask* 1 Clock input Clock enable Power supply Ground Open* 2 1. DQMB0: DQ0 to DQ7 DQMB1: DQ8 to DQ15 DQMB2: DQ16 to DQ23 DQMB3: DQ24 to DQ31 DQMB4: DQ32 to DQ39 DQMB5: DQ40 to DQ47 DQMB6: DQ48 to DQ55 DQMB7: DQ56 to DQ63 2. Don't connect. Internally connected with die.
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HM5225645F-B60, HM5225325F-B60
Pin Arrangement (HM5225325F)
108-bump BGA 1 A B C D E F G H J K L
DQ31
2
NC
3
NC
4
DQ24
5
VSS
6
DQ23
7
NC
8
NC
9
DQ16
DQ30
NC
NC
DQ25
VCC
DQ22
NC
NC
DQ17
DQ29
NC
NC
DQ26
VCC
DQ21
NC
NC
DQ18
DQ28 DQ MB3
NC
NC
DQ27
VSS
DQ20
NC
NC DQ MB2 RAS
DQ19
NC
NC
CKE
VCC
WE
A12
VCC
A10
A13
A7
A5
VCC
A1
A4
VSS
A2
A3
A8
A6
VSS
A0
A11
VSS
A9
CS
M Open N P R T U
NC
CLK
VCC
CAS
DQ MB0 NC NC DQ4 VSS DQ11 NC
NC
DQ MB1 DQ12
DQ3
NC
DQ2
NC
NC
DQ5
VCC
DQ10
NC
NC
DQ13
DQ1
NC
NC
DQ6
VCC
DQ9
NC
NC
DQ14
DQ0
NC
NC
DQ7
VSS
DQ8
NC
NC
DQ15
(Top view)
5
HM5225645F-B60, HM5225325F-B60
Pin Description (HM5225325F)
Pin name A0 to A13 Function Address input Row address Column address A0 to A11 A0 to A8
Bank select address A12/A13 (BS) DQ0 to DQ31 CS RAS CAS WE DQMB0 to DQMB3 CLK CKE VCC VSS Open NC Note: Data-input/output Chip select Row address strobe command Column address strobe command Write enable Byte data mask* 1 Clock input Clock enable Power supply Ground Open* 2 No connection*3 1. DQMB0: DQ0 to DQ7 DQMB1: DQ8 to DQ15 DQMB2: DQ16 to DQ23 DQMB3: DQ24 to DQ31 2. Don't connect. Internally connected with die. 3. Not internally connected with die.
6
HM5225645F-B60, HM5225325F-B60
Block Diagram (HM5225645F)
14
A0 to A13 CS RAS CAS WE CLK CKE
64-Mbit SDRAM 4M x 16
64-Mbit SDRAM 4M x 16
64-Mbit SDRAM 4M x 16
64-Mbit SDRAM 4M x 16
8 DQMB 0 to DQMB 7 64 DQ 0 to DQ 63
2
16
2
16
2
16
2
16
Block Diagram (HM5225325F)
14
A0 to A13 CS RAS CAS WE CLK CKE
64-Mbit SDRAM 8M x 8
64-Mbit SDRAM 8M x 8
64-Mbit SDRAM 8M x 8
64-Mbit SDRAM 8M x 8
DQMB 0 to DQMB 3 32 DQ 0 to DQ 31
4
1
8
1
8
1
8
1
8
7
HM5225645F-B60, HM5225325F-B60
Power-up Sequence and Initialization Sequence
Power up sequence 100 s VCC CKE, DQMB CLK CS, DQ 0V Low Low Low
Power stabilize
Initialization sequence 200 s
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Operating temperature Storage temperature Note: 1. Respect to V SS Symbol VT VCC Iout Topr Tstg Value -0.5 to VCC + 0.5 ( 4.6 (max)) -0.5 to +4.6 50 0 to +70 (Tj max = 110) -55 to +125 Unit V V mA C C Note 1 1
DC Operating Conditions (Tcase = 0 to +70C [Tj max = 110C])
Parameter Supply voltage Symbol VCC VSS Input high voltage Input low voltage Notes: 1. 2. 3. 4. 5. VIH VIL Min 3.0 0 2.0 -0.3 Max 3.6 0 VCC + 0.3 0.8 Unit V V V V Notes 1, 2 3 1, 4 1, 5
All voltage referred to VSS The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. VIH (max) = VCC + 2.0 V for pulse width 3 ns at VCC. VIL (min) = VSS - 2.0 V for pulse width 3 ns at VSS .
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HM5225645F-B60, HM5225325F-B60
DC Characteristics (Tcase = 0 to 70C [Tj max = 110C]), VCC = 3.3 V 0.3 V, VSS = 0 V) (HM5225645F)
HM5225645F -B60 Parameter Operating current (CAS latency = 2) (CAS latency = 3) Standby current in power down Standby current in power down (input signal stable) Standby current in non power down Standby current in non power down (input signal stable) Active standby current in power down Active standby current in power down (input signal stable) Active standby current in non power down Active standby current in non power down (input signal stable) Burst operating current (CAS latency = 2) (CAS latency = 3) Refresh current Self refresh current Self refresh current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage Symbol I CC1 I CC1 I CC2P I CC2PS I CC2N I CC2NS I CC3P I CC3PS I CC3N I CC3NS Min -- -- -- -- -- -- -- -- -- -- Max 200 220 12 8 64 36 16 12 80 60 Unit mA mA mA mA mA mA mA mA mA mA CKE = VIL, t CK = 12 ns CKE = VIL, t CK = CKE, CS = VIH, t CK = 12 ns CKE = VIH, t CK = CKE = VIL, t CK = 12 ns CKE = VIL, t CK = CKE, CS = VIH, t CK = 12 ns CKE = VIH, t CK = 6 7 4 9 1, 2, 6 2, 7 1, 2, 4 2, 9 Test conditions Burst length = 1 t RC = min Notes 1, 2, 3
I CC4 I CC4 I CC5 I CC6 I CC6 I LI I LO VOH VOL
-- -- -- -- -- -4 -6 2.4 --
220 270 380 4 1.6 4 6 -- 0.4
mA mA mA mA mA A A V V
t CK = min, BL = 4
1, 2, 5
t RC = min VIH VCC - 0.2 V VIL 0.2 V 0 Vin VCC 0 Vout VCC DQ = disable I OH = -4 mA I OL = 4 mA
3 8
9
HM5225645F-B60, HM5225325F-B60
DC Characteristics (Tcase = 0 to 70C [Tj max = 110C]), VCC = 3.3 V 0.3 V, VSS = 0 V) (HM5225325F)
HM5225325F -B60 Parameter Operating current (CAS latency = 2) (CAS latency = 3) Standby current in power down Standby current in power down (input signal stable) Standby current in non power down Standby current in non power down (input signal stable) Active standby current in power down Active standby current in power down (input signal stable) Active standby current in non power down Active standby current in non power down (input signal stable) Burst operating current (CAS latency = 2) (CAS latency = 3) Refresh current Self refresh current Self refresh current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage Symbol I CC1 I CC1 I CC2P I CC2PS I CC2N I CC2NS I CC3P I CC3PS I CC3N I CC3NS Min -- -- -- -- -- -- -- -- -- -- Max 180 200 12 8 64 36 16 12 80 60 Unit mA mA mA mA mA mA mA mA mA mA CKE = VIL, t CK = 12 ns CKE = VIL, t CK = CKE, CS = VIH, t CK = 12 ns CKE = VIH, t CK = CKE = VIL, t CK = 12 ns CKE = VIL, t CK = CKE, CS = VIH, t CK = 12 ns CKE = VIH, t CK = 6 7 4 9 1, 2, 6 2, 7 1, 2, 4 2, 9 Test conditions Burst length = 1 t RC = min Notes 1, 2, 3
I CC4 I CC4 I CC5 I CC6 I CC6 I LI I LO VOH VOL
-- -- -- -- -- -4 -6 2.4 --
200 250 380 4 1.6 4 6 -- 0.4
mA mA mA mA mA A A V V
t CK = min, BL = 4
1, 2, 5
t RC = min VIH VCC - 0.2 V VIL 0.2 V 0 Vin VCC 0 Vout VCC DQ = disable I OH = -4 mA I OL = 4 mA
3 8
10
HM5225645F-B60, HM5225325F-B60
Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CLK operating current. 7. After power down mode, no CLK operating current. 8. After self refresh mode set, self refresh current. 9. Input signals are V IH or VIL fixed.
Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V)
Parameter Input capacitance (CLK) Input capacitance (Input except DQM) Input capacitance (DQM) Output capacitance (DQ) Notes: 1. 2. 3. 4. Symbol CI1 CI2 CI3 CO Min 10 10 2.5 3 Max 14 14 5 5 Unit pF pF pF pF Notes 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 3, 4
Capacitance measured with Boonton Meter or effective capacitance measuring method. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing. DQMB = VIH to disable Dout. This parameter is sampled and not 100% tested.
11
HM5225645F-B60, HM5225325F-B60
AC Characteristics (Tcase = 0 to 70C [Tj max = 110C]), VCC = 3.3 V 0.3 V, VSS = 0 V)
HM5225645F/HM5225325F -B60 Parameter System clock cycle time (CAS latency = 2) (CAS latency = 3) CLK high pulse width CLK low pulse width Access time from CLK (CAS latency = 2) (CAS latency = 3) Data-out hold time CLK to Data-out low impedance CLK to Data-out high impedance (CAS latency = 2, 3) Input setup time CKE setup time for power down exit Input hold time HITACHI Symbol t CK t CK t CKH t CKL t AC t AC t OH t LZ t HZ t AS , t CS, t DS, Tsi t CES t CESP Tpde PC/100 Symbol Tclk Tclk Tch Tcl Tac Tac Toh Min 15 10 3 3 -- -- 3 2 -- 2 2 1 70 50 20 20 10 20 1 -- Max -- -- -- -- 8 6 -- -- 6 -- -- -- -- 120000 -- -- -- -- 5 64 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 1, 2 1, 2, 3 1, 4 1, 5, 6 1 1, 5 1 1 1 1 1 1 1 1 1, 2 Notes 1
t AH, t CH, t DH, Thi t CEH Trc Tras Trcd Trp Tdpl Trrd
Ref/Active to Ref/Active command t RC period Active to Precharge command period Active command to column command (same bank) Precharge to active command period Write recovery or data-in to precharge lead time Active (a) to Active (b) command period Transition time (rise and fall) Refresh period t RAS t RCD t RP t DPL t RRD tT t REF
12
HM5225645F-B60, HM5225325F-B60
Notes: 1. 2. 3. 4. 5. 6. AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V. Access time is measured at 1.5 V. Load condition is CL = 50 pF. t LZ (min) defines the time at which the outputs achieves the low impedance state. t HZ (max) defines the time at which the outputs achieves the high impedance state. t CES define CKE setup time to CLK rising edge except power down exit command. t AS /tAH: Address, tCS/tCH: CS, RAS, CAS, WE, DQM. t DS/tDH: Data-in, tCES/tCEH: CKE
Test Conditions * Input and output timing reference levels: 1.5 V * Input waveform and output load: See following figures
2.4 V
input
0.4 V
2.0 V 0.8 V
I/O CL t
T
tT
13
HM5225645F-B60, HM5225325F-B60
Package Dimensions
HM5225645FBP Series HM5225325FBP Series (BP-108)
Unit: mm
Preliminary
0.20
0.35 C
-C-
4xC1.2
14.00
4x
A -A987654321 A B C D E F G H J K L M N P R T U 1.27
Pin 1 Index 21.0 0.10
-B13.0 0.10
0.60
2.10
108x 0.75 0.30 M C A B 0.15 M C
2.35 Max
Details of the part A
Hitachi Code JEDEC EIAJ Weight (reference value)
1.27
0.15 C
22.00
BP-108 -- -- 1.2 g
14
HM5225645F-B60, HM5225325F-B60
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to:
Hitachi Europe GmbH Electronic components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX
Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223
Copyright (c) Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
15
HM5225645F-B60, HM5225325F-B60
Revision Record
Rev. Date 0.0 0.1 Feb. 1, 1999 Contents of Modification Initial issue Drawn by S. Hatano S. Hatano Approved by S. Hatano S. Hatano
Feb. 19, 1999 Pin arrangement Correct pin No. to JEDEC standard Package dimenssion Correct illustration and indexes
0.2 1.0
Apr. 1, 1999 Oct. 1, 1999
Ordering information Correct error of type No. Programmable CAS latency: 3 to 2/3 Ordering information Addition of note Pin description Addition of note 1 DC Characteristics (HM5225645F) I CC1 max (CL = 2): 280 mA to 200 mA I CC1 max (CL = 3): 300 mA to 220 mA I CC4 max (CL = 2): 280 mA to 220 mA I CC4 max (CL = 3): 360 mA to 270 mA I CC5 max: 460 mA to 380 mA DC Characteristics (HM5225325F) I CC1 max (CL = 2): 260 mA to 180 mA I CC1 max (CL = 3): 280 mA to 200 mA I CC4 max (CL = 2): 260 mA to 200 mA I CC4 max (CL = 3): 320 mA to 250 mA I CC5 max: 460 mA to 380 mA Capacitance CI1 max: 16 pF to 14 pF CI2 max: 20 pF to 14 pF CO min: 4 pF to 3 pF CO max: 6.5 pF to 5 pF Package dimension Change tolerance of height
S. Hatano
S. Hatano
16

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